Increased performance of circuit devices on a substrate (e.g., integrated circuit (IC) transistors, resistors, capacitors, etc. on a semiconductor substrate) is usually a major factor considered during design, manufacture, and operation of those devices. For example, during design and manufacture or forming of, metal oxide semiconductor (MOS) transistor semiconductor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often desired to increase movement of electrons in N-type MOS device (NMOS) channel regions and to increase movement of positive charged holes in P-type MOS device (PMOS) channel regions.
One method of reducing the overall resistance of a MOS device is to dope the area between the source/drain regions and the channel region, known as the tip regions of a MOS device. For instance, a dopant may be implanted in the source/drain regions and an anneal may be carried out to diffuse the dopant towards the channel region.
Because an implant and diffusion method is used, the ability to control the dopant concentration and location is limited. Furthermore, the size of other parts of a MOS device, such as the thickness of its offset spacers, can also have a great impact on the location of the tip regions. All of this, in turn, affects the ability of the tip regions to maximize dopant concentration and come into close proximity of the channel region. Accordingly, improved methods or structures are needed to overcome the limitations of conventional tip regions.